1. Field of the Invention
The invention relates to a crack-stopping structure and method for forming the same, and more particularly, to a wafer crack-stopping hollow structure and method for forming the same.
2. Description of the Prior Art
In the field of semiconductor device fabrication, semiconductor devices and interconnections are formed to construct integrated circuits (ICs) on a semiconductor wafer. The fabrication of ICs may be completed through different methods and steps, but generally involves depositing layers of conductive, semiconductor, and insulating materials in precise patterns on a substrate or wafer to form the desired circuit or array patterns. Once formed, the ICs then need to be separated into individual piece-parts, so called dies or chips. The dies, which are isolated or separated from each other by scribe lines, are then separated by sawing along the scribe lines and are individually packaged.
When processing the semiconductor wafer to form multi-layer structures, alignment marks are typically disposed in the scribe lines for aligning the wafer with the mask. The alignment marks usually include metal or polysilicon that are formed on and beneath an uppermost surface of the semiconductor wafer. On the other hand, testing circuits are often simultaneously fabricated on the wafer along with the actual devices. The testing circuits include a plurality of metal test pads, which are electrically connected to an external terminal through probe needles, located on the scribe lines.
It is found that when the semiconductor wafer is diced, the dicing tool such as a dicing saw usually cuts across the alignment marks and the test pads. A major consideration is that the stress resulted from the sawing process causes serious peeling at where the large metal, that is the alignment marks and test pads occupied. This results in delamination and/or cracking at the interface between the multiple layers and it extends into neighboring dies. Consequently, delamination and/or cracking impact the reliability of the ICs and hence a reduction in IC yield from a given semiconductor wafer.